1. Field of the Invention
The present invention relates to semiconductor integrated circuits, and more particularly to electrostatic discharge (ESD) protection circuits that protect a power supply boundary circuit from electrostatic discharge surge inputs applied to external terminals. It is applied to, for example, to low-power-supply-voltage complementary metal oxide semiconductor (CMOS) large-scale integrated circuits (LSIs).
2. Description of the Related Art
For example, in a CMOS LSI, an ESD protection circuit is connected between external terminals and an internal circuit in order to protect an input circuit and an output circuit from destruction due to ESD. Voltage clamp devices for ESD protection may be a diode, a transistor, or a silicon controlled rectifier (SCR).
Since the operational voltage of an SCR is generally high, when an ESD protection circuit using an SCR is applied to a miniaturized CMOS LSI with power supply of lowered voltage, it is desirable to achieve low-voltage trigger to protect MOS transistors with low gate-withstand voltage to improve their reliability.
It should be noted that a mixed-signal LSI generally contains analog circuitry vulnerable to noise signal interference, a low-voltage differential signaling (LVDS) circuit operable at high speed, and a dynamic semiconductor memory (embedded DRAM), etc. Power supply domains for such circuits are separated by the power-line separation technique and/or ground-line separation technique, and circuits belonging to different power supply domains exchange signals with each other. The techniques are effective because they reduce interference by noise signals among circuits and can set circuits in inactive power supply domains to a standby state, etc., and therefore are necessary.
In the conventional LSI with power supply domains separated by power-line separation technique and/or ground-line separation technique, when a surge current due to an ESD stress flows from a power supply terminal of one power supply domain to that of another power supply domain, the largest voltage is applied to power supply boundary devices (e.g., MOS devices) used for a circuit that carries a signal between different power supply domains. It is important to design an ESD protection circuit network to reduce the voltage below the withstand voltage of the MOS devices to prevent their gates from destruction. Since the current of an ampere order flows into the ESD protection circuit network when ESD stress is applied, it is important to consider not only ESD protection devices but parasitic resistance of interconnects in the network. On the other hand, withstand voltages of MOS transistors tend to fall with progress of the microfabrication technology of semiconductor integrated circuits, which makes the design of the ESD protection circuit network more difficult.
As a conventional art to prevent destruction of power supply boundary devices, the applicant of the present application proposed to use a detector circuit which consists of an inverter circuit, etc., to detect ESD applied to the power supply terminal (see U.S. Pat. No. 7,307,822). Since the threshold of the inverter circuit decides the detection threshold of ESD according to the technology, the detection threshold of ESD can be set by design, and it is easy to avoid malfunction by a power supply or ground bounce, etc. Moreover, the input circuit and output circuit which are used as power supply boundary circuits serve as simple inverter circuits in normal operation, and detection of ESD by the detector circuit generates an ESD detection signal which controls the connection among the input or output circuits to perform protection operation (ESD stress relief operation) for power supply boundary devices.
In the circuit of the U.S. Pat. No. 7,307,822 Publication, when an ESD stress is applied, a voltage of the same polarity as the normal power supply application is applied only to one of the two power supply domain circuits. Thus a detector circuit, an input circuit, and an output circuit only in the power supply domain function normally.
However, it is necessary to provide detector circuits in both of separated power supply domains in order to detect ESD stresses in both directions, therefore, the output signal line of each detector circuit must be independent to result in complicated signal traces.
Moreover, U.S. Pat. No. 7,352,547 discloses other conventional examples for preventing destruction of power supply boundary devices. The publication discloses that turning-on of a MOSFET in accordance with the potential difference between two points in the electric discharging path through which a surge current flows when ESD is applied to result in eased ESD stress on the power supply boundary devices. With this technology, the detection threshold voltage substantially equals to the threshold voltage of the MOSFET, and therefore it is difficult to freely set the detection threshold of ESD and to avoid malfunction by ground bounce, etc.